Through silicon via copper electrodeposition for 3D integration R Beica, C Sharbono, T Ritzdorf 2008 58th Electronic Components and Technology Conference, 577-583, 2008 | 145 | 2008 |
Warpage and thermal characterization of fan-out wafer-level packaging JH Lau, M Li, D Tian, N Fan, E Kuah, W Kai, M Li, J Hao, YM Cheung, Z Li, ... IEEE transactions on components, packaging and manufacturing technology 7 …, 2017 | 143 | 2017 |
Design, materials, process, fabrication, and reliability of fan-out wafer-level packaging JH Lau, M Li, QM Li, I Xu, T Chen, Z Li, KH Tan, QX Yong, Z Cheng, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 8 (6 …, 2018 | 84 | 2018 |
Fan-out wafer-level packaging for heterogeneous integration JH Lau, M Li, ML Qingqian, T Chen, I Xu, QX Yong, Z Cheng, N Fan, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 8 (9 …, 2018 | 81 | 2018 |
Advanced metallization for 3D integration R Beica, P Siblerud, C Sharbono, M Bernt 2008 10th Electronics Packaging Technology Conference, 212-218, 2008 | 63 | 2008 |
Chip-first fan-out panel-level packaging for heterogeneous integration CT Ko, H Yang, JH Lau, M Li, M Li, C Lin, JW Lin, T Chen, I Xu, CL Chang, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 8 (9 …, 2018 | 57 | 2018 |
Warpage measurements and characterizations of fan-out wafer-level packaging with large chips and multiple redistributed layers JH Lau, M Li, L Yang, M Li, I Xu, T Chen, S Chen, QX Yong, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 8 …, 2018 | 55 | 2018 |
Through-silicon-via technology for 3D integration J Dukovic, S Ramaswami, S Pamarthy, R Yalamanchili, N Rajagopalan, ... 2010 IEEE International Memory Workshop, 1-2, 2010 | 39 | 2010 |
Electroplating compositions and methods R Beica, ND Brown, K Wang US Patent 7,151,049, 2006 | 32 | 2006 |
Copper electrodeposition for 3D integration R Beica, C Sharbono, T Ritzdorf 2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, 127-131, 2008 | 31 | 2008 |
3D integration: Applications and market trends R Beica 2015 International 3D Systems Integration Conference (3DIC), TS5. 1.1-TS5. 1.7, 2015 | 30 | 2015 |
Design, materials, process, and fabrication of fan-out panel-level heterogeneous integration CT Ko, H Yang, J Lau, M Li, M Li, C Lin, JW Lin, CL Chang, JY Pan, ... Journal of Microelectronics and Electronic Packaging 15 (4), 141-147, 2018 | 25 | 2018 |
Reliability of fan-out wafer-level packaging with large chips and multiple re-distributed layers J Lau, M Li, L Yang, M Li, QX Yong, Z Cheng, T Chen, I Xu, N Fan, E Kuah, ... 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 1574-1582, 2018 | 22 | 2018 |
3D technology applications market trends & key challenges A Pizzagalli, T Buisson, R Beica 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014 …, 2014 | 19 | 2014 |
Flip chip market and technology trends R Beica 2013 Eurpoean Microelectronics Packaging Conference (EMPC), 1-4, 2013 | 19 | 2013 |
Reliability of fan-out wafer-level heterogeneous integration J Lau, M Li, Y Lei, M Li, I Xu, T Chen, QX Yong, Z Cheng, W Kai, P Lo, Z Li, ... International Symposium on Microelectronics 2018 (1), 000224-000232, 2018 | 18 | 2018 |
Control of breakdown products in electroplating baths LA Gomez, R Beica, D Morrissey, EN Step US Patent 6,508,924, 2003 | 16 | 2003 |
Seed layer recovery D Morrissey, J Calvert, R Beica US Patent App. 09/977,596, 2002 | 16 | 2002 |
Soft gold electroplating from a non-cyanide bath for electronic applications K Wang, R Beica, N Brown IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology …, 2004 | 13 | 2004 |
Characterizations of fan-out wafer-level packaging M Li, Q Li, J Lau, N Fan, E Kuah, W Kai, K Cheung, Z Li, KH Tan, I Xu, ... International Symposium on Microelectronics 2017 (1), 000557-000562, 2017 | 12 | 2017 |