Ilker Hamzaoglu
Title
Cited by
Cited by
Year
Test set compaction algorithms for combinational circuits
I Hamzaoglu, JH Patel
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998
5961998
Reducing test application time for full scan embedded cores
I Hamzaoglu, JH Patel
Digest of Papers. Twenty-Ninth Annual International Symposium on Fault …, 1999
4421999
Scalable, distributed data mining-an agent architecture
H Kargupta, I Hamzaoglu, B Stafford
Proceedings Third International Conference on Knowledge Discovery and Data …, 1997
2201997
New techniques for deterministic test pattern generation
I Hamzaoglu, JH Patel
Journal of Electronic Testing 15 (1), 63-73, 1999
1981999
Reducing test application time for built-in-self-test test pattern generators
I Hamzaoglu, JH Patel
VLSI Test Symposium, 2000. Proceedings. 18th IEEE, 369-375, 2000
782000
A high performance deblocking filter hardware for high efficiency video coding
E Ozcan, Y Adibelli, I Hamzaoglu
IEEE Transactions on Consumer Electronics 59 (3), 714-720, 2013
612013
A high performance and low energy intra prediction hardware for high efficiency video coding
E Kalali, Y Adibelli, I Hamzaoglu
22nd International Conference on Field Programmable Logic and Applications …, 2012
542012
An efficient hardware architecture for H. 264 intra prediction algorithm
E Sahin, I Hamzaoglu
Proceedings of the conference on Design, automation and test in Europe, 183-188, 2007
502007
Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation
O Tasdizen, A Akin, H Kukner, I Hamzaoglu
IEEE Transactions on Consumer Electronics 55 (3), 1645-1653, 2009
492009
Compact two-pattern test set generation for combinational and full scan circuits
I Hamzaoglu, JH Patel
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
491998
Low power H. 264 deblocking filter hardware implementations
M Parlak, I Hamzaoglu
IEEE Transactions on Consumer Electronics 54 (2), 808-816, 2008
462008
A low energy HEVC inverse transform hardware
E Kalali, E Ozcan, OM Yalcinkaya, I Hamzaoglu
IEEE Transactions on Consumer Electronics 60 (4), 754-761, 2014
422014
Efficient hardware implementations of low bit depth motion estimation algorithms
A Celebi, O Urhan, I Hamzaoglu, S Erturk
IEEE Signal Processing Letters 16 (6), 513-516, 2009
422009
A novel computational complexity and power reduction technique for H. 264 intra prediction
M Parlak, Y Adibelli, I Hamzaoglu
IEEE Transactions on Consumer Electronics 54 (4), 2006-2014, 2008
402008
A computation and energy reduction technique for HEVC discrete cosine transform
E Kalali, AC Mert, I Hamzaoglu
IEEE Transactions on Consumer Electronics 62 (2), 166-174, 2016
392016
An adaptive true motion estimation algorithm for frame rate conversion of high definition video and its hardware implementations
M Çetin, İ Hamzaoğlu
IEEE Transactions on Consumer Electronics 57 (2), 923-931, 2011
362011
An efficient hardware architecture for quarter-pixel accurate H. 264 motion estimation
S Oktem, I Hamzaoglu
10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007
362007
A high performance hardware architecture for an SAD reuse based hierarchical motion estimation algorithm for H. 264 video coding
S Yalcin, HF Ates, I Hamzaoglu
International Conference on Field Programmable Logic and Applications, 2005 …, 2005
362005
A low energy HEVC sub-pixel interpolation hardware
E Kalali, I Hamzaoglu
2014 IEEE International Conference on Image Processing (ICIP), 1218-1222, 2014
342014
A high performance hardware architecture for half-pixel accurate H. 264 motion estimation
S Yalcin, I Hamzaoglu
2006 IFIP International Conference on Very Large Scale Integration, 63-67, 2006
342006
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