| ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars A Shafiee, A Nag, N Muralimanohar, R Balasubramonian, JP Strachan, ... Proceedings of the 43rd International Symposium on Computer Architecture, 14-26, 2016 | 1063 | 2016 |
| CACTI 6.0: A tool to model large caches N Muralimanohar, R Balasubramonian, NP Jouppi HP Laboratories, 22-31, 2009 | 903 | 2009 |
| Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0 N Muralimanohar, R Balasubramonian, N Jouppi Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007 | 710 | 2007 |
| Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures R Balasubramonian, D Albonesi, A Buyuktosunoglu, S Dwarkadas Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000 | 544 | 2000 |
| Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling G Semeraro, G Magklis, R Balasubramonian, DH Albonesi, S Dwarkadas, ... Proceedings Eighth International Symposium on High Performance Computer …, 2002 | 543 | 2002 |
| Rethinking DRAM design and organization for energy-constrained multi-cores AN Udipi, N Muralimanohar, N Chatterjee, R Balasubramonian, A Davis, ... Proceedings of the 37th annual international symposium on Computer …, 2010 | 328 | 2010 |
| Reducing the complexity of the register file in dynamic superscalar processors R Balasubramonian, S Dwarkadas, DH Albonesi Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International …, 2001 | 307 | 2001 |
| Overcoming the challenges of crossbar resistive memory architectures C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 295 | 2015 |
| Micro-pages: increasing DRAM efficiency with locality-aware data placement K Sudan, N Chatterjee, D Nellans, M Awasthi, R Balasubramonian, ... ACM SIGARCH Computer Architecture News 38 (1), 219-230, 2010 | 289 | 2010 |
| NDC: Analyzing the impact of 3D-stacked memory+ logic devices on MapReduce workloads SH Pugsley, J Jestes, H Zhang, R Balasubramonian, V Srinivasan, ... Performance Analysis of Systems and Software (ISPASS), 2014 IEEE …, 2014 | 249 | 2014 |
| Near-Data Processing: Insights from a MICRO-46 Workshop R Balasubramonian, J Chang, T Manning, JH Moreno, R Murphy, R Nair, ... Micro, IEEE 34 (4), 36-42, 2014 | 223 | 2014 |
| Multiple clock domain microprocessor D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ... US Patent 7,089,443, 2006 | 219* | 2006 |
| Multiple clock domain microprocessor D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ... US Patent 7,089,443, 2006 | 219* | 2006 |
| Dynamically tuning processor resources with adaptive processing DH Albonesi, R Balasubramonian, SG Dropsbo, S Dwarkadas, ... Computer 36 (12), 49-58, 2003 | 201 | 2003 |
| Multiple clock domain microprocessor D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ... US Patent 7,739,537, 2010 | 197 | 2010 |
| Leveraging 3D technology for improved reliability N Madan, R Balasubramonian Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007 | 193 | 2007 |
| CHOP: Adaptive filter-based dram caching for CMP server platforms X Jiang, N Madan, L Zhao, M Upton, R Iyer, S Makineni, D Newell, ... High Performance Computer Architecture (HPCA), 2010 IEEE 16th International …, 2010 | 179 | 2010 |
| USIMM: the Utah SImulated Memory Module N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ... Technical report, University of Utah, 2012. UUCS-12-002, 2012 | 172 | 2012 |
| Handling the problems and opportunities posed by multiple on-chip memory controllers M Awasthi, DW Nellans, K Sudan, R Balasubramonian, A Davis Proceedings of the 19th international conference on Parallel architectures …, 2010 | 168 | 2010 |
| Integrating adaptive on-chip storage structures for reduced dynamic power S Dropsho, A Buyuktosunoglu, R Balasubramonian, DH Albonesi, ... Parallel Architectures and Compilation Techniques, 2002. Proceedings. 2002 …, 2002 | 164 | 2002 |
Naveen MuralimanoharHP LabsVerified email at hpe.com
