| Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs Y Cheng, L Zhang, Y Han, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 239-249, 2012 | 68 | 2012 |
| Compact model of subvolume MTJ and its design application at nanoscale technology nodes Y Zhang, B Yan, W Kang, Y Cheng, JO Klein, Y Zhang, Y Chen, W Zhao IEEE Transactions on Electron Devices 62 (6), 2048-2055, 2015 | 66 | 2015 |
| A radiation hardened hybrid spintronic/CMOS nonvolatile unit using magnetic tunnel junctions W Zhao, E Deng, JO Klein, Y Cheng, D Ravelosona, Y Zhang, C Chappert Journal of Physics D: Applied Physics 47 (40), 405003, 2014 | 52 | 2014 |
| Architecture design with STT-RAM: Opportunities and challenges P Chi, S Li, Y Cheng, Y Lu, SH Kang, Y Xie 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 109-114, 2016 | 34 | 2016 |
| Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach J Yang, P Wang, Y Zhang, Y Cheng, W Zhao, Y Chen, HH Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 31 | 2015 |
| Temperature impact analysis and access reliability enhancement for 1T1MTJ STT-RAM B Wu, Y Cheng, J Yang, A Todri-Sanial, W Zhao IEEE Transactions on Reliability 65 (4), 1755-1768, 2016 | 25 | 2016 |
| Building energy-efficient multi-level cell STT-RAM caches with data compression L Liu, P Chi, S Li, Y Cheng, Y Xie 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 751-756, 2017 | 16 | 2017 |
| STT-RAM buffer design for precision-tunable general-purpose neural network accelerator L Song, Y Wang, Y Han, H Li, Y Cheng, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2017 | 14 | 2017 |
| Quantitative evaluation of reliability and performance for STT-MRAM L Zhang, A Todri-Sanial, W Kang, Y Zhang, L Torres, Y Cheng, W Zhao 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1150-1153, 2016 | 13 | 2016 |
| Wrapper chain design for testing TSVs minimization in circuit-partitioned 3D SoC Y Cheng, L Zhang, Y Han, J Liu, X Li 2011 Asian Test Symposium, 181-186, 2011 | 13 | 2011 |
| Reliability and performance evaluation for STT-MRAM under temperature variation L Zhang, Y Cheng, W Kang, Y Zhang, L Torres, W Zhao, A Todri-Sanial 2016 17th International Conference on Thermal, Mechanical and Multi-Physics …, 2016 | 11 | 2016 |
| HARS: a high-performance reliable routing scheme for 3D NoCs J Zhou, H Li, Y Fang, T Wang, Y Cheng, X Li 2014 IEEE Computer Society Annual Symposium on VLSI, 392-397, 2014 | 11 | 2014 |
| A study of 3-D power delivery networks with multiple clock domains A Todri-Sanial, Y Cheng IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (11 …, 2016 | 10 | 2016 |
| Readability challenges in deeply scaled STT-MRAM W Kang, Y Cheng, Y Zhang, D Ravelosona, W Zhao 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2014 | 10 | 2014 |
| An adaptive 3T-3MTJ memory cell design for STT-MRAM-based LLCs L Xue, B Wu, B Zhang, Y Cheng, P Wang, C Park, J Kan, SH Kang, Y Xie IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 484-495, 2018 | 9 | 2018 |
| Odesy: a novel 3t-3mtj cell design with optimized area density, scalability and latency L Xue, Y Cheng, J Yang, P Wang, Y Xie 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 8 | 2016 |
| A body-biasing of readout circuit for STT-RAM with improved thermal reliability L Yang, Y Cheng, Y Wang, H Yu, W Zhao, A Todri-Sanial 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1530-1533, 2015 | 8 | 2015 |
| A novel method to mitigate TSV electromigration for 3D ICs Y Cheng, A Todri-Sanial, A Bosio, L Dillio, P Girard, A Virazel, P Vevet, ... 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 121-126, 2013 | 8 | 2013 |
| TSV Minimization for Circuit—Partitioned 3D SoC Test Wrapper Design YQ Cheng, L Zhang, YH Han, XW Li Journal of computer science and technology 28 (1), 119-128, 2013 | 8 | 2013 |
| Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect Y Cheng, A Todri-Sanial, J Yang, W Zhao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (11 …, 2016 | 7 | 2016 |
