Indradeep Ghosh
Indradeep Ghosh
Verified email at us.fujitsu.com
Title
Cited by
Cited by
Year
GKLEE: concolic verification and test generation for GPUs
G Li, P Li, G Sawaya, G Gopalakrishnan, I Ghosh, SP Rajan
Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of …, 2012
1242012
A fast and low-cost testing technique for core-based system-chips
I Ghosh, S Dey, NK Jha
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000
1152000
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
I Ghosh, A Raghunathan, NK Jha
IEEE transactions on computer-aided design of integrated circuits and …, 1997
1091997
KLOVER: A symbolic execution and automatic test generation tool for C++ programs
G Li, I Ghosh, SP Rajan
International Conference on Computer Aided Verification, 609-615, 2011
1082011
Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams
I Ghosh, M Fujita
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
952001
A design-for-testability technique for register-transfer level circuits using control/data flow extraction
I Ghosh, A Raghunathan, NK Jha
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
831998
SymJS: automatic symbolic testing of JavaScript web applications
G Li, E Andreasen, I Ghosh
Proceedings of the 22nd ACM SIGSOFT International Symposium on Foundations …, 2014
802014
A low overhead design for testability and test generation technique for core-based systems
I Ghosh, NK Jha, S Dey
Proceedings International Test Conference 1997, 50-59, 1997
721997
Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits
S Bhawmik, I Ghosh, N Jha
US Patent 6,463,560, 2002
672002
Efficient sequential ATPG for functional RTL circuits
L Zhang, I Ghosh, M Hsiao
ITC 3, 290-298, 2003
642003
A design for testability technique for RTL circuits using control/data flow extraction
I Ghosh, A Raghunathan, NK Jha
Proceedings of International Conference on Computer Aided Design, 329-336, 1996
561996
JST: An automatic test generation tool for industrial Java applications with strings
I Ghosh, N Shafiei, G Li, WF Chiang
2013 35th International Conference on Software Engineering (ICSE), 992-1001, 2013
522013
Hierarchical test generation and design for testability methods for ASPPs and ASIPs
I Ghosh, A Raghunathan, NK Jha
IEEE transactions on computer-aided design of integrated circuits and …, 1999
461999
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
I Ghosh, M Fujita
Proceedings of the 37th Annual Design Automation Conference, 43-48, 2000
442000
A BIST scheme for RTL circuits based on symbolic testability analysis
I Ghosh, NK Jha, S Bhawmik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000
432000
PASS: string solving with parameterized array and interval automaton
G Li, I Ghosh
Haifa Verification Conference, 15-31, 2013
412013
A low overhead design for testability and test generation technique for core-based systems-on-a-chip
I Ghosh, NK Jha, S Dey
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
411999
Symbolic execution and test generation for GPU programs
G Li, SP Rajan, I Ghosh
US Patent 8,595,701, 2013
392013
Using symbolic execution to check global temporal requirements in an application
MR Prasad, I Ghosh, SP Rajan
US Patent 8,359,576, 2013
352013
Technique for efficient parallelization of software analysis in a distributed computing environment through intelligent dynamic load balancing
I Ghosh, MR Prasad
US Patent 8,763,001, 2014
342014
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