Peter Cappello
Peter Cappello
Professor of Computer Science, University of California, Santa Barbara
Verified email at cs.ucsb.edu
Title
Cited by
Cited by
Year
Javelin: Internet‐based parallel computing using Java
BO Christiansen, P Cappello, MF Ionescu, MO Neary, KE Schauser, D Wu
Concurrency: Practice and Experience 9 (11), 1139-1160, 1997
3421997
Unifying VLSI Array Designs with Geometric Transformations.
PR Cappello, K Steiglitz
ICPP, 448-457, 1983
1501983
Unifying VLSI array design with linear transformations of space-time
PR Cappello, K Steiglitz
Advances in computing research 2, 23-65, 1984
1361984
Javelin++: scalability issues in global computing
MO Neary, SP Brydon, P Kmiec, S Rollins, P Cappello
Concurrency: Practice and Experience 12 (8), 727-753, 2000
1172000
Javelin++: scalability issues in global computing
MO Neary, SP Brydon, P Kmiec, S Rollins, P Cappello
Concurrency: Practice and Experience 12 (8), 727-753, 2000
1172000
Some complexity issues in digital signal processing
P Cappello, K Steiglitz
IEEE Transactions on Acoustics, Speech, and Signal Processing 32 (5), 1037-1041, 1984
1171984
Javelin 2.0: Java-based parallel computing on the Internet
MO Neary, A Phipps, S Richman, P Cappello
European Conference on Parallel Processing, 1231-1238, 2000
1072000
Systolic architectures for vector quantization
GA Davidson, PR Cappello, A Gersho
IEEE Transactions on Acoustics, Speech, and Signal Processing 36 (10), 1651-1664, 1988
971988
Systolic super summation device
PR Cappello, WL Miranker
US Patent 4,751,665, 1988
961988
Javelin: Parallel computing on the internet
MO Neary, BO Christiansen, P Cappello, KE Schauser
Future Generation Computer Systems 15 (5-6), 659-674, 1999
911999
Advanced eager scheduling for Java‐based adaptive parallel computing
MO Neary, P Cappello
Concurrency and Computation: Practice and Experience 17 (7‐8), 797-819, 2005
902005
Advanced eager scheduling for Java‐based adaptive parallel computing
MO Neary, P Cappello
Concurrency and Computation: Practice and Experience 17 (7‐8), 797-819, 2005
902005
Easily testable iterative logic arrays
CW Wu, PR Cappello
IEEE Transactions on Computers 39 (5), 640-652, 1990
861990
A VLSI layout for a pipelined Dadda multiplier
PR Cappello, K Steiglitz
ACM Transactions on Computer Systems (TOCS) 1 (2), 157-174, 1983
741983
Digital signal processing applications of systolic algorithms
PR Cappello, K Steiglitz
VLSI systems and computations, 245-254, 1981
631981
A processor-time minimal systolic array for transitive closure
CJ Scheiman, PR Cappello
[1990] Proceedings of the International Conference on Application Specific …, 1990
611990
A processor-time minimal systolic array for transitive closure
CJ Scheiman, PR Cappello
[1990] Proceedings of the International Conference on Application Specific …, 1990
611990
Implementing the beam and warming method on the hypercube
J Bruno, PR Cappello
Proceedings of the third conference on Hypercube concurrent computers and …, 1989
581989
Converting affine recurrence equations to quasi-uniform recurrence equations
Y Yaacoby, PR Cappello
Aegean Workshop on Computing, 319-328, 1988
491988
Scheduling a system of affine recurrence equations onto a systolic array
Y Yaacoby, PR Cappello
Proceedings. International Conference on Systolic Arrays, 373,374,375,376 …, 1988
491988
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