| A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging K Mistry, C Allen, C Auth, B Beattie, D Bergstrom, M Bost, M Brazier, ... 2007 IEEE International Electron Devices Meeting, 247-250, 2007 | 1700 | 2007 |
| A 90-nm logic technology featuring strained-silicon SE Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, ... IEEE Transactions on electron devices 51 (11), 1790-1797, 2004 | 915 | 2004 |
| A logic nanotechnology featuring strained-silicon SE Thompson, M Armstrong, C Auth, S Cea, R Chau, G Glass, T Hoffman, ... IEEE Electron Device Letters 25 (4), 191-193, 2004 | 686 | 2004 |
| 45nm high-k+ metal gate strain-enhanced transistors C Auth, A Cappellani, JS Chun, A Dalis, A Davis, T Ghani, G Glass, ... 2008 Symposium on VLSI Technology, 128-129, 2008 | 572 | 2008 |
| ASAP7: A 7-nm finFET predictive process design kit LT Clark, V Vashishtha, L Shifren, A Gujja, S Sinha, B Cline, ... Microelectronics Journal 53, 105-115, 2016 | 484 | 2016 |
| Fabrication and operation of correlated electron material devices CAP de ARAUJO, JB Celinska, KG Reid, L Shifren | 201 | 2018 |
| Physics of hole transport in strained silicon MOSFET inversion layers EX Wang, P Matagne, L Shifren, B Obradovic, R Kotlyar, S Cea, M Stettler, ... IEEE Transactions on Electron Devices 53 (8), 1840-1851, 2006 | 174 | 2006 |
| A Wigner function-based quantum ensemble Monte Carlo study of a resonant tunneling diode L Shifren, C Ringhofer, DK Ferry IEEE Transactions on Electron Devices 50 (3), 769-773, 2003 | 143 | 2003 |
| Advanced Transistors with Threshold Voltage Set Dopant Structures L Shifren, P Ranade, L Scudder US Patent App. 12/895,785, 2011 | 141 | 2011 |
| Transistor with threshold voltage set notch and method of fabrication thereof R Arghavani, P Ranade, L Shifren, SE Thompson, C De Villeneuve US Patent 8,759,872, 2014 | 130 | 2014 |
| Low power semiconductor transistor structure and method of fabrication thereof L Shifren, P Ranade, SE Thompson, SR Sonkusale, W Zhang US Patent 8,530,286, 2013 | 115 | 2013 |
| Wrap-around contacts for finfet and tri-gate devices SM Cea, R Mehandru, L Shifren, K Kuhn US Patent App. 12/646,651, 2011 | 110 | 2011 |
| Method, system and device for complementary non-volatile memory device operation A Bhavnagarwala, RC Aitken, L Shifren US Patent 9,589,636, 2017 | 94 | 2017 |
| Correlated electron switch programmable fabric L Shifren, G Yeric, S Sinha, B Cline, V Chandra US Patent 10,056,143, 2018 | 92 | 2018 |
| Advanced channel engineering achieving aggressive reduction of VTvariation for ultra-low-power applications K Fujita, Y Torii, M Hori, J Oh, L Shifren, P Ranade, M Nakagawa, ... 2011 International Electron Devices Meeting, 32.3. 1-32.3. 4, 2011 | 90 | 2011 |
| Correlated electron switch L Shifren US Patent 9,735,766, 2017 | 89 | 2017 |
| Device and technology implications of the Internet of Things R Aitken, V Chandra, J Myers, B Sandhu, L Shifren, G Yeric 2014 symposium on VLSI technology (VLSI-technology): digest of technical …, 2014 | 84 | 2014 |
| High performance Hi-K+ metal gate strain enhanced transistors on (110) silicon P Packan, S Cea, H Deshpande, T Ghani, M Giles, O Golonzka, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 84 | 2008 |
| Method, system and device for non-volatile memory device operation RC Aitken, L Shifren US Patent 9,558,819, 2017 | 81 | 2017 |
| Particle Monte Carlo simulation of Wigner function tunneling L Shifren, DK Ferry Physics Letters A 285 (3-4), 217-221, 2001 | 74 | 2001 |
