Subhendu Roy
Subhendu Roy
Cadence Design Systems
utexas.edu üzerinde doğrulanmış e-posta adresine sahip
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
Clock tree resynthesis for multi-corner multi-mode timing closure
S Roy, PM Mattheakis, L Masse-Navette, DZ Pan
IEEE transactions on computer-aided design of integrated circuits and …, 2015
372015
Design for manufacturability and reliability in extreme-scaling VLSI
B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan
Science China Information Sciences 59 (6), 1-23, 2016
342016
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
S Roy, MR Choudhury, R Puri, DZ Pan
Design Automation Conference, 2013
332013
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs
S Roy, M Choudhury, R Puri, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
182015
LRR-DPUF: Learning resilient and reliable digital physical unclonable function
J Miao, M Li, S Roy, B Yu
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
172016
Triple patterning lithography layout decomposition using end-cutting
B Yu, S Roy, JR Gao, DZ Pan
Journal of Micro/Nanolithography, MEMS, and MOEMS 14 (1), 011002, 2014
152014
OSFA: A new paradigm of aging aware gate-sizing for power/performance optimizations under multiple operating conditions
S Roy, D Liu, J Singh, J Um, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
142016
Reliability aware gate sizing combating NBTI and oxide breakdown
S Roy, DZ Pan
VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 …, 2014
142014
SD-PUF: Spliced digital physical unclonable function
J Miao, M Li, S Roy, Y Ma, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
92017
Cross-layer optimization for high speed adders: A pareto driven machine learning approach
Y Ma, S Roy, J Miao, J Chen, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
72018
OSFA: A new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions
S Roy, D Liu, J Um, DZ Pan
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
72015
Automated synthesis of high-performance two operand binary parallel prefix adder
M Choudhury, R Puri, S Roy, SC Sundararajan
US Patent 8,527,920, 2013
72013
Evolving challenges and techniques for nanometer SoC clock network synthesis
S Roy, PM Mattheakis, L Masse-Navette, DZ Pan
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE …, 2014
62014
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders
S Roy, Y Ma, J Miao, B Yu
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
42017
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction
CH Lin, S Roy, CY Wang, DZ Pan, D Chen
2015 33rd IEEE International Conference on Computer Design (ICCD), 236-243, 2015
42015
Skew bounded buffer tree resynthesis for clock power optimization
S Roy, DZ Pan, PM Mattheakis, PS Colyer, L Masse-Navette, PO Ribet
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 87-90, 2015
42015
Large Scale VLSI Circuit Simulation Using Point Relaxation
S Roy, Y Save, S Patkar, H Narayanan
CSC, 2010
32010
Logic and clock network optimization in nanometer VLSI circuits
S Roy
The University of Texas at Austin, 2015
22015
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory
U Roy, T Pramanik, S Roy, A Chatterjee, LF Register, SK Banerjee
ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (3 …, 2021
2021
Machine learning for variability aware statistical device design: The case of perpendicular spin-transfer-torque random access memory
U Roy, T Pramanik, S Roy, LF Register, SK Banerjee
2017 75th Annual Device Research Conference (DRC), 1-2, 2017
2017
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