| Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits K Roy, S Mukhopadhyay, H Mahmoodi-Meimand Proceedings of the IEEE 91 (2), 305-327, 2003 | 2735 | 2003 |
| Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS S Mukhopadhyay, H Mahmoodi, K Roy IEEE transactions on computer-aided design of integrated circuits and …, 2005 | 566 | 2005 |
| Neurocube: A programmable digital neuromorphic architecture with high-density 3D memory D Kim, J Kung, S Chai, S Yalamanchili, S Mukhopadhyay ACM SIGARCH Computer Architecture News 44 (3), 380-392, 2016 | 266 | 2016 |
| A circuit-compatible model of ballistic carbon nanotube field-effect transistors A Raychowdhury, S Mukhopadhyay, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 260 | 2004 |
| Process variation in embedded memories: failure analysis and variation aware architecture A Agarwal, BC Paul, S Mukhopadhyay, K Roy IEEE Journal of Solid-State Circuits 40 (9), 1804-1814, 2005 | 203 | 2005 |
| Gate leakage reduction for scaled devices using transistor stacking S Mukhopadhyay, C Neau, RT Cakici, A Agarwal, CH Kim, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (4), 716-730, 2003 | 195 | 2003 |
| Leakage power analysis and reduction for nanoscale circuits A Agarwal, S Mukhopadhyay, A Raychowdhury, K Roy, CH Kim IEeE Micro 26 (2), 68-80, 2006 | 185 | 2006 |
| Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits H Mahmoodi, S Mukhopadhyay, K Roy IEEE Journal of Solid-State Circuits 40 (9), 1787-1796, 2005 | 181 | 2005 |
| Low-power scan design using first-level supply gating S Bhunia, H Mahmoodi, D Ghosh, S Mukhopadhyay, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (3), 384-395, 2005 | 167 | 2005 |
| Statistical design and optimization of SRAM cell for yield enhancement S Mukhopadhyay, H Mahmoodi, K Roy IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 160 | 2004 |
| Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation S Mukhopadhyay, K Roy Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 160 | 2003 |
| Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling S Mukhopadhyay, A Raychowdhury, K Roy Proceedings of the 40th annual Design Automation Conference, 169-174, 2003 | 158 | 2003 |
| A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations CH Kim, JJ Kim, S Mukhopadhyay, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (3), 349-357, 2005 | 132 | 2005 |
| Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile S Mukhopadhyay, A Raychowdhury, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 125 | 2005 |
| An energy efficient cache design using spin torque transfer (STT) RAM M Rasquinha, D Choudhary, S Chatterjee, S Mukhopadhyay, ... 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design …, 2010 | 122 | 2010 |
| Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale era A Bansal, S Mukhopadhyay, K Roy IEEE Transactions on Electron Devices 54 (6), 1409-1419, 2007 | 112 | 2007 |
| Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement S Mukhopadhyay, H Mahmoodi-Meimand, K Roy 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 111 | 2004 |
| Process variations and process-tolerant design S Bhunia, S Mukhopadhyay, K Roy 20th international conference on VLSI design held jointly with 6th …, 2007 | 98 | 2007 |
| Design of a process variation tolerant self-repairing SRAM for yield enhancement in nanoscaled CMOS S Mukhopadhyay, K Kim, H Mahmoodi, K Roy IEEE Journal of Solid-State Circuits 42 (6), 1370-1382, 2007 | 96 | 2007 |
| Fast and accurate analytical modeling of through-silicon-via capacitive coupling DH Kim, S Mukhopadhyay, SK Lim IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (2 …, 2011 | 94 | 2011 |
