Nikolas Ioannou
Nikolas Ioannou
Research Manager, IBM Research Zurich
Verified email at zurich.ibm.com - Homepage
Title
Cited by
Cited by
Year
Phase-based application-driven hierarchical power management on the single-chip cloud computer
N Ioannou, M Kauschke, M Gries, M Cintra
2011 International Conference on Parallel Architectures and Compilation†…, 2011
632011
Combining thread level speculation helper threads and runahead execution
P Xekalakis, N Ioannou, M Cintra
Proceedings of the 23rd international conference on Supercomputing, 410-420, 2009
512009
Crail: A High-Performance I/O Architecture for Distributed Data Processing.
P Stuedi, A Trivedi, J Pfefferle, R Stoica, B Metzler, N Ioannou, I Koltsidas
IEEE Data Eng. Bull. 40 (1), 38-49, 2017
452017
Wear leveling of a memory array
TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ...
US Patent 9,857,986, 2018
442018
Reaping the performance of fast {NVM} storage with udepot
K Kourtis, N Ioannou, I Koltsidas
17th {USENIX} Conference on File and Storage Technologies ({FAST} 19), 1-15, 2019
382019
Cooperative data deduplication in a solid state storage array
TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic
US Patent 10,013,169, 2018
342018
Vertical sub-micron CMOS transistors on (110),(111),(311),(511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same
L Forbes, W Noble, A Reinberg
US Patent App. 10/222,997, 2004
332004
On the [ir] relevance of network performance for data processing
A Trivedi, P Stuedi, J Pfefferle, R Stoica, B Metzler, I Koltsidas, N Ioannou
8th {USENIX} Workshop on Hot Topics in Cloud Computing (HotCloud 16), 2016
322016
Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
CJ Camp, TJ Fisher, AD Fry, N Ioannou, R Pletka, S Tomic
US Patent 9,563,373, 2017
272017
Two-level hierarchical log structured array architecture with minimized write amplification
R Haas, N Ioannou, I Koltsidas, RA Pletka, AD Walls
US Patent 9,619,158, 2017
262017
Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,251,909, 2016
24*2016
Toward a more accurate understanding of the limits of the TLS execution paradigm
N Ioannou, J Singer, S Khan, P Xekalakis, P Yiapanis, A Pocock, G Brown, ...
IEEE International Symposium on Workload Characterization (IISWC'10), 1-12, 2010
232010
Snap ML: A hierarchical framework for machine learning
C DŁnner, T Parnell, D Sarigiannis, N Ioannou, A Anghel, G Ravi, ...
arXiv preprint arXiv:1803.06333, 2018
202018
Cache allocation in a computerized system
XY Hu, N Ioannou, I Koltsidas
US Patent 9,342,458, 2016
202016
From random block corruption to privilege escalation: A filesystem attack vector for rowhammer-like attacks
A Kurmus, N Ioannou, M Neugschwandtner, N Papandreou, T Parnell
11th {USENIX} Workshop on Offensive Technologies ({WOOT} 17), 2017
192017
Non-volatile memory controller cache architecture with support for separation of data streams
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic, ...
US Patent 9,779,021, 2017
182017
Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 9,632,927, 2017
182017
Flow control valve that may be used for mold temperature control systems
HK Wieder
US Patent 6,854,705, 2005
172005
Deep learning acceleration based on in-memory computing
E Eleftheriou, M Le Gallo, SR Nandakumar, C Piveteau, I Boybat, V Joshi, ...
IBM Journal of Research and Development 63 (6), 7: 1-7: 16, 2019
152019
Flash-conscious cache population for enterprise database workloads
H Kim, I Koltsidas, N Ioannou, S Seshadri, P Muench, CL Dickey, L Chiu
ADMS@ VLDB, 2014
152014
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Articles 1–20