| Fast node merging with don't cares using logic implications YC Chen, CY Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 31 | 2010 |
| Fast detection of node mergers using logic implications YC Chen, CY Wang Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 30 | 2009 |
| Automated mapping for reconfigurable single-electron transistor arrays YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 878-883, 2011 | 27 | 2011 |
| On synthesizing memristor-based logic circuits with minimal operational pulses HP Wang, CC Lin, CC Wu, YC Chen, CY Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 25 | 2018 |
| LOOPLock: LOgic OPtimization based Cyclic Logic Locking HY Chiang, YC Chen, DX Ji, XM Yang, CC Lin, CY Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019 | 22 | 2019 |
| Node addition and removal in the presence of don't cares YC Chen, CY Wang Proceedings of the 47th Design Automation Conference, 505-510, 2010 | 21 | 2010 |
| A synthesis algorithm for reconfigurable single-electron transistor arrays YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (1), 1-20, 2013 | 20 | 2013 |
| On reconfigurable single-electron transistor arrays synthesis using reordering techniques CE Chiang, LF Tang, CY Wang, CY Huang, YC Chen, S Datta, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 19 | 2013 |
| Enhancements to SAT attack: Speedup and breaking cyclic logic encryption YC Chen ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (4 …, 2018 | 16 | 2018 |
| Majority logic circuits optimisation by node merging CC Chung, YC Chen, CY Wang, CC Wu 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 714-719, 2017 | 16 | 2017 |
| Rewiring for threshold logic circuit minimization CC Lin, CY Wang, YC Chen, CY Huang Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 …, 2014 | 16 | 2014 |
| Logic restructuring using node addition and removal YC Chen, CY Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 16 | 2012 |
| Fast synthesis of threshold logic networks with optimization YC Chen, R Wang, YP Chang 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 486-491, 2016 | 15 | 2016 |
| Verification of reconfigurable binary decision diagram-based single-electron transistor arrays YC Chen, CY Wang, CY Huang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 14 | 2013 |
| Synthesis and verification of cyclic combinational circuits JH Chen, YC Chen, WC Weng, CY Huang, CY Wang 2015 28th IEEE International System-on-Chip Conference (SOCC), 257-262, 2015 | 13 | 2015 |
| Width minimization in the single-electron transistor array synthesis CW Liu, CE Chiang, CY Huang, CY Wang, YC Chen, S Datta, ... 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 13 | 2014 |
| A probabilistic analysis method for functional qualification under mutation analysis HY Lin, CY Wang, SC Chang, YC Chen, HM Chou, CY Huang, YC Yang, ... 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 147-152, 2012 | 12 | 2012 |
| A novel ACO-based pattern generation for peak power estimation in VLSI circuits YL Liu, CY Wang, YC Chen, YH Chang 2009 10th International Symposium on Quality Electronic Design, 317-323, 2009 | 10 | 2009 |
| Tree-based logic encryption for resisting SAT attack YC Chen 2017 IEEE 26th Asian Test Symposium (ATS), 46-51, 2017 | 9 | 2017 |
| Sensitization criterion for threshold logic circuits and its application CK Tsai, CY Wang, CY Huang, YC Chen 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 226-233, 2013 | 9 | 2013 |
