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Yung-Chih Chen
Yung-Chih Chen
Associate Professor of Department of Electrical Engineering, National Taiwan University of Science
Verified email at mail.ntust.edu.tw - Homepage
Title
Cited by
Cited by
Year
Fast node merging with don't cares using logic implications
YC Chen, CY Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
282010
Fast detection of node mergers using logic implications
YC Chen, CY Wang
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
282009
Automated mapping for reconfigurable single-electron transistor arrays
YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan
2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 878-883, 2011
272011
Node addition and removal in the presence of don't cares
YC Chen, CY Wang
Proceedings of the 47th Design Automation Conference, 505-510, 2010
212010
A synthesis algorithm for reconfigurable single-electron transistor arrays
YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (1), 1-20, 2013
202013
On synthesizing memristor-based logic circuits with minimal operational pulses
HP Wang, CC Lin, CC Wu, YC Chen, CY Wang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
192018
On reconfigurable single-electron transistor arrays synthesis using reordering techniques
CE Chiang, LF Tang, CY Wang, CY Huang, YC Chen, S Datta, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
192013
Logic restructuring using node addition and removal
YC Chen, CY Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
162012
Rewiring for threshold logic circuit minimization
CC Lin, CY Wang, YC Chen, CY Huang
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 …, 2014
152014
Verification of reconfigurable binary decision diagram-based single-electron transistor arrays
YC Chen, CY Wang, CY Huang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
142013
Enhancements to SAT attack: Speedup and breaking cyclic logic encryption
YC Chen
ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (4 …, 2018
132018
Fast synthesis of threshold logic networks with optimization
YC Chen, R Wang, YP Chang
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 486-491, 2016
132016
Width minimization in the single-electron transistor array synthesis
CW Liu, CE Chiang, CY Huang, CY Wang, YC Chen, S Datta, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
122014
Majority logic circuits optimisation by node merging
CC Chung, YC Chen, CY Wang, CC Wu
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 714-719, 2017
112017
Synthesis and verification of cyclic combinational circuits
JH Chen, YC Chen, WC Weng, CY Huang, CY Wang
2015 28th IEEE International System-on-Chip Conference (SOCC), 257-262, 2015
112015
A probabilistic analysis method for functional qualification under mutation analysis
HY Lin, CY Wang, SC Chang, YC Chen, HM Chou, CY Huang, YC Yang, ...
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 147-152, 2012
112012
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
YL Liu, CY Wang, YC Chen, YH Chang
2009 10th International Symposium on Quality Electronic Design, 317-323, 2009
102009
LOOPLock: LOgic OPtimization based Cyclic Logic Locking
HY Chiang, YC Chen, DX Ji, XM Yang, CC Lin, CY Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019
82019
Sensitization criterion for threshold logic circuits and its application
CK Tsai, CY Wang, CY Huang, YC Chen
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 226-233, 2013
82013
An improved approach for alternative wires identification
YC Chen, CY Wang
2005 International Conference on Computer Design, 711-716, 2005
82005
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