| Enhancement-mode GaAs MOSFETs with an In0. 3 Ga0. 7As channel, a mobility of over 5000 cm2/V· s, and transconductance of over 475 μS/μm RJW Hill, DAJ Moran, X Li, H Zhou, D Macintyre, S Thoms, A Asenov, ... IEEE Electron Device Letters 28 (12), 1080-1082, 2007 | 230 | 2007 |
| High mobility III-V MOSFETs for RF and digital applications M Passlack, P Zurcher, K Rajagopalan, R Droopad, J Abrokwah, M Tutt, ... 2007 IEEE International Electron Devices Meeting, 621-624, 2007 | 108 | 2007 |
| GaAs on Si epitaxy by aspect ratio trapping: Analysis and reduction of defects propagating along the trench direction T Orzali, A Vert, B O'Brien, JL Herman, S Vivekanand, RJW Hill, Z Karim, ... Journal of Applied Physics 118 (10), 2015 | 69 | 2015 |
| Threshold voltage shift due to charge trapping in dielectric-gated AlGaN/GaN high electron mobility transistors examined in Au-free technology DW Johnson, RTP Lee, RJW Hill, MH Wong, G Bersuker, EL Piner, ... IEEE transactions on electron devices 60 (10), 3197-3203, 2013 | 67 | 2013 |
| Positive bias instability and recovery in InGaAs channel nMOSFETs S Deora, G Bersuker, WY Loh, D Veksler, K Matthews, TW Kim, RTP Lee, ... IEEE Transactions on Device and Materials Reliability 13 (4), 507-514, 2013 | 53 | 2013 |
| Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow RJW Hill, C Park, J Barnett, J Price, J Huang, N Goel, WY Loh, J Oh, ... 2010 International Electron Devices Meeting, 6.2. 1-6.2. 4, 2010 | 49 | 2010 |
| Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications TW Kim, DH Kim, DH Koh, HM Kwon, RH Baek, D Veksler, C Huffman, ... 2013 IEEE International Electron Devices Meeting, 16.3. 1-16.3. 4, 2013 | 43 | 2013 |
| ETB-QW InAs MOSFET with scaled body for improved electrostatics TW Kim, DH Kim, DH Koh, RJW Hill, RTP Lee, MH Wong, T Cunningham, ... 2012 International Electron Devices Meeting, 32.3. 1-32.3. 4, 2012 | 41 | 2012 |
| 1 µm gate length, In0. 75Ga0. 25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 µS/μm RJW Hill, R Droopad, DAJ Moran, X Li, H Zhou, D Macintyre, S Thoms, ... Electronics Letters 44 (7), 498-500, 2008 | 39* | 2008 |
| Review of current status of III-V MOSFETs I Thayne, R Hill, M Holland, X Li, H Zhou, D Macintyre, S Thoms, K Kalna, ... ECS transactions 19 (5), 275, 2009 | 36 | 2009 |
| InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax TW Kim, RJW Hill, CD Young, D Veksler, L Morassi, S Oktybrshky, J Oh, ... 2012 Symposium on VLSI Technology (VLSIT), 179-180, 2012 | 35 | 2012 |
| A study of capping layers for sulfur monolayer doping on III-V junctions JH Yum, HS Shin, R Hill, J Oh, HD Lee, RM Mushinski, TW Hudnall, ... Applied Physics Letters 101 (25), 2012 | 30 | 2012 |
| Defect reduction in epitaxial InP on nanostructured Si (001) substrates with position-controlled seed arrays Q Li, KW Ng, CW Tang, KM Lau, R Hill, A Vert Journal of crystal growth 405, 81-86, 2014 | 29 | 2014 |
| Memory arrays, and methods of forming memory arrays D Daycock, RJ Hill, C Larsen, W Kim, JB Dorhout, BD Lowe, JD Hopkins, ... US Patent 10,083,981, 2018 | 28 | 2018 |
| High-Speed E-Mode InAs QW MOSFETs With Insulator for Future RF Applications DH Kim, TW Kim, RJW Hill, CD Young, CY Kang, C Hobbs, P Kirsch, ... IEEE electron device letters 34 (2), 196-198, 2013 | 26 | 2013 |
| Gallium oxide (Ga2 O3) on gallium arsenide—A low defect, high-K system for future devices GW Paterson, JA Wilson, D Moran, R Hill, AR Long, I Thayne, M Passlack, ... Materials Science and Engineering: B 135 (3), 277-281, 2006 | 26 | 2006 |
| Monte Carlo Simulations of High-Performance Implant Free InGaAs Nano-MOSFETs for Low-Power CMOS Applications K Kalna, JA Wilson, DAJ Moran, RJW Hill, AR Long, R Droopad, ... IEEE transactions on nanotechnology 6 (1), 106-112, 2007 | 25 | 2007 |
| Study of piezoresistance under unixial stress for technologically relevant III-V semiconductors using wafer bending experiments A Nainani, J Yum, J Barnett, R Hill, N Goel, J Huang, P Majhi, R Jammy, ... Applied Physics Letters 96 (24), 2010 | 22 | 2010 |
| A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III–V MOSFETs X Li, RJW Hill, H Zhou, CDW Wilkinson, IG Thayne Microelectronic Engineering 85 (5-6), 996-999, 2008 | 22 | 2008 |
| Heavily tellurium doped n-type InGaAs grown by MOCVD on 300 mm Si wafers T Orzali, A Vert, RTP Lee, A Norvilas, G Huang, JL Herman, RJW Hill, ... Journal of crystal Growth 426, 243-247, 2015 | 19 | 2015 |
a asenovThe University of GlasgowVerified email at glasgow.ac.uk
