| Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization Y Wang, M Orshansky, C Caramanis Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 63 | 2014 |
| Lattice PUF: A strong physical unclonable function provably secure against machine learning attacks Y Wang, X Xi, M Orshansky 2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020 | 31 | 2020 |
| A new maskless debiasing method for lightweight physical unclonable functions A Aysu, Y Wang, P Schaumont, M Orshansky 2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017 | 22 | 2017 |
| PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation Y Wang, C Caramanis, M Orshansky 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 6 | 2016 |
| A monte carlo simulation flow for seu analysis of sequential circuits M Li, Y Wang, M Orshansky Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 5 | 2016 |
| Efficient helper data reduction in SRAM PUFs via lossy compression Y Wang, M Orshansky 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 4 | 2018 |
| Novel power grid reduction method based on l1 regularization Y Wang, M Li, X Yi, Z Song, M Orshansky, C Caramanis Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 4 | 2015 |
| Exploiting randomness in sketching for efficient hardware implementation of machine learning applications Y Wang, C Caramanis, M Orshansky 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 2 | 2016 |
